1. Field of the Invention
The invention relates generally to a substrate bias generating circuit and, more particularly, to a substrate bias generating circuit driven in response to an externally applied clock signal. The invention has particular applicability to dynamic random access memories (DRAMs).
2. Description of the Background Art
Generally, a semiconductor device such as a dynamic random access memory (referred to as "DRAM" hereinafter) and a static random access memory (SRAM) is constituted by many MOS transistors formed on a semiconductor substrate. In such a semiconductor device, normally, it is desirable to maintain a potential of a semiconductor substrate to be constantly within a predetermined range. The reason will be described below.
FIG. 5 is a block diagram of a semiconductor integrated circuit device in general. Referring to FIG. 5, the semiconductor device 100 comprises a function circuit (or an internal circuit) formed on a single semiconductor substrate and a substrate bias generating circuit 120. Function circuit 110 is constituted by many MOS transistors in order to implement functions needed in semiconductor device 100. Semiconductor bias generating circuit 120 is also constituted by MOS transistors and generates a substrate bias voltage V.sub.BB in order to maintain a semiconductor substrate 130 at a predetermined negative potential.
FIG. 6 shows one part of a cross sectional structure of a general semiconductor integrated circuit device. Function circuit 110 shown in FIG. 5 also comprises the cross sectional structure shown in FIG. 6. A MOS transistor and interconnection formed on the periphery thereof are shown as one example in FIG. 6. Referring to FIG. 6, a MOS transistor comprises N type impurity regions 131 and 132 forming a source and a drain formed close to a main surface of a P type semiconductor substrate 130, and a gate electrode 133. A gate oxide film 134 is formed between gate electrode 133 and substrate 130. A channel is formed between source region 131 and drain region 132 depending on a voltage applied to gate electrode 133. An N type impurity region 135 forming an interconnection region is formed to be spaced apart from impurity region 131 and close to substrate 130. On a surface of substrate 130 between impurity regions 131 and 135, a signal line 136 is formed with a thick filter insulating film 137 interposed therebetween.
In operation, when the MOS transistor is rendered conductive, hot electron-hole pairs are generated in the vicinity of drain 132. Most of the generated hot electrons flow into drain 132. Most of holes flow into substrate 130. A potential of substrate 130 rises as a result. The rise of a potential of substrate 130 causes the following problems.
PN junctions are formed between source region 131 and P type substrate 130 and between drain region 132 and P type substrate 130. These PN junctions are brought into a forward biased state. In addition, a PN junction between interconnection region 135 and substrate 130 is also brought into a forward biased state. Therefore, leakage current flows between source region 131 and substrate 130, between drain region 132 and substrate 130, between interconnection region 135 and substrate 130. As a result, the channel between source region 131 and drain region 132 is not formed or a signal transmitted through interconnection region 135 is delayed.
In addition, when a signal at a high level, that is, a power supply voltage level is transmitted through interconnection 136, a channel depending on a potential of interconnection 136 is liable to be formed close to the surface of substrate 130 between impurity regions 131 and 135 by the rise of a potential of substrate 130. That is to say, a parasitic MOS transistor is formed by interconnection 136, insulating film 137, N type regions 131 and 135. When the parasitic transistor operates, the normal operation of function circuit 110 shown in FIG. 5 is prevented.
Additionally it should be pointed out that the rise of a potential of substrate 130 changes a threshold voltage Vth of a MOS transistor. FIG. 7 is a graph showing a relationship between a threshold voltage Vth of an NMOS transistor formed on a P type semiconductor substrate and a potential V.sub.BB of a P type semiconductor substrate. Referring to FIG. 7, when substrate potential V.sub.BB is in a low range, that is, -V1&lt;V.sub.BB &lt;-V2, threshold voltage Vth is kept almost constant. When substrate potential V.sub.BB rises (V.sub.BB &gt;-V1), however, threshold voltage Vth varies in response to a value of V.sub.BB. This implies that the rise of substrate potential V.sub.BB prevents the MOS transistor from performing stable operation. In other words, function circuit 110 shown in FIG. 5 causes malfunction by the rise of substrate potential V.sub.BB.
Therefore, in order to prevent the above problems, a substrate bias generating circuit 120 is provided to keep potential V.sub.BB of substrate 130 in a predetermined range (- V1&lt;V.sub.BB &lt;-V2).
The substrate bias generating circuit is also provided for a DRAM, for example. FIG. 8 is a block diagram of a conventional DRAM. Referring to FIG. 8, the DRAM 1 comprises a memory cell array 85 including many memory cells, an address buffer 81 receiving externally applied address signals A0 through An, a row decoder 82 and a column decoder 83 for designating a row and a column of memory cell array 85, respectively, in response to the received address signals, and a sense amplifier 84 for amplifying a data signal read from a memory cell. An input data Di is applied through a data in buffer 86. An output data Do is output through a data out buffer 87. DRAM 1 comprises a clock generator 88 generating a clock signal for controlling various circuits provided therein.
The DRAM further comprises two substrate bias generating circuits 89 and 93 for generating the above mentioned substrate bias voltage V.sub.BB. Substrate bias generating circuit 89 comprises a ring oscillator not shown, and is constantly driven by a clock signal generated from the ring oscillator after a power supply voltage Vcc is supplied.
Substrate bias generating circuit 93 is driven by an externally applied row address strobe signal /RAS. RAS input buffer 92 receives an externally supplied signal /RAS and applies the received signal to clock generator 88 and substrate bias generating circuit 93. Circuit 93 is driven by the applied signal and generates substrate bias voltage V.sub.BB.
The reason why DRAM 1 comprises circuit 93 in addition to substrate bias generating circuit 89 will be stated below. Generally, a DRAM is brought into a standby state and an active state in response to externally applied clock signals /RAS and /CAS, etc. In the active state, a normal read operation, a write operation, a read modify write operation, a static column mode operation, a page mode operation, etc. are performed. In the activating state, many circuits within DRAM 1 shown in FIG. 8 are activated, while only a few circuits are activated in a standby state. This implies that, compared to the standby state, a substrate potential is likely to rise in the activating state. Therefore, it is necessary to maintain the substrate potential more firmly at a low potential in the active state. Hence, circuit 93 driven in the active state and generating substrate bias voltage V.sub.BB is additionally provided. Circuit 93 is driven by a signal /RAS varying frequently in the active state. Although in the example shown in FIG. 8, substrate bias generating circuit 93 is driven by signal /RAS, circuit 93 may be driven by an externally applied column address strobe signal /CAS in some cases.
Substrate bias generating circuit 93 driven by signal /RAS was described above. A substrate bias generating circuit 95 driven by an address transition detection (referred to as "ATD" hereinafter) pulse is provided in some cases. An ATD circuit 94 detects a transition of external address signals A0 through An applied to an address buffer 81 and generates an ATD pulse. Substrate bias generating circuit 95 is driven by the ATD pulse and generates voltage V.sub.BB. Substrate bias generating circuit 95 generates voltage V.sub.BB in the active state of DRAM 1 similarly to circuit 93; however, circuit 95 is particularly characterized in that it can generate voltage V.sub.BB even when a signal /RAS does not vary as in a static column mode. Even though the static column mode is included as the activating state, circuit 93 is not driven because signal /RAS is constant in this mode. However, the ATD pulse is generated even in this mode, so that circuit 95 can generate voltage V.sub.BB. It is pointed out that a conventional DRAM comprises either circuits 93 or 95 in addition to substrate bias generating circuit 89.
DRAMs and SRAMs are employed in various electrical appliances such as a personal computer. Since, particularly in recent years, many DRAMs are used in portable electrical appliances such as a notebook type personal computer, it is strongly desired that power consumed by a DRAM is reduced. Therefore, it is pointed out that there is a need to decrease power consumption also in a substrate bias generating circuit.
FIG. 9 is a circuit diagram of substrate bias generating circuit 93 shown in FIG. 8. Referring to FIG. 9, the substrate bias generating circuit 93 comprises cascaded inverters 25 and 26 for shaping a waveform of an input clock signal .phi.4, a NAND gate 16 for outputting clock signals inverted from each other, a NOR gate 17, an inverter 18, and two charge pump circuits 50 and 51. Externally applied signal /RAS is received by RAS input buffer 92. The received input signal /RAS is applied to clock generator 88. Input signal /RAS is applied also to substrate bias generating circuit 93 as the above mentioned signal .phi.4.
FIG. 10 is a timing chart for describing operation of substrate bias generating circuit 93 shown in FIG. 9. Referring to FIGS. 9 and 10, the operation of substrate bias generating circuit 93 will be described below. Input clock signal .phi.4 is applied, so that a potential of node E changes as shown in FIG. 10. Therefore, potentials of an output node F of NAND gate 16 and an output node C of NOR gate 17 also change as shown in FIG. 10. Since an output signal of NOR gate 17 is inverted by inverter 18, an output node G of inverter 18 changes as shown in FIG. 10. Charge pump circuits 50 and 51 respectively receive clock signals which are obtained from input clock signal .phi.4 and inverted from each other.
Charge pump circuit 50 comprises a capacitor 20 connected in series between output node G of inverter 18 and substrate 130, and a PMOS transistor 23. A PMOS transistor 24 is connected between a connection node I of capacitor 20 and transistor 23, and ground. Similarly, charge pump circuit 51 also comprises a capacitor 19 and a PMOS transistor 21 connected in series between output node F of NAND gate 16 and substrate 130. A PMOS transistor 22 is connected between a connection node H of capacitor 19 and transistor 21, and ground. Each of transistors 23 and 21 is diode connected. The on and off of transistor 22 is controlled by a potential of node I. The on and off of transistor 24 is controlled by a potential of node H. An output voltage of NAND gate 16 is applied to back gates of transistors 21 and 22. An output voltage of inverter 18 is applied to back gates of transistors 23 and 24.
In charge pump circuit 50, when a potential of node G falls from power supply potential Vcc to a ground potential, a potential of node I also start to fall by coupling of capacitor 20. On the other hand, in charge pump circuit 51, when a potential of node F rises from ground potential to power supply potential Vcc, a potential of node H starts to rise by coupling of capacitor 19. When transistor 24 is turned on by the rise of a potential of node H, a discharging path of capacitor 20 is cut off and negative charges discharged from capacitor 20 start to be stored in node I. As a result, a potential of node I starts to fall below the ground potential and finally becomes a negative potential having the same value as that of power supply potential Vcc (=-Vcc). Therefore, transistor 23 is turned on, so that a voltage (=-Vcc+Vthp) higher than the potential of node I (=-Vcc) by threshold voltage Vthp of a PMOS transistor is applied to substrate 103 as substrate bias voltage V.sub.BB. Transistor 22 is rendered conductive in response to a fall of the potential of node I, so that the potential of node H is higher than a potential of node K (=-Vcc+Vthp). Therefore, transistor 21 is turned off. Transistor 23 is rendered conductive, so that a negative voltage (=-Vcc+Vthp) is supplied to substrate 130 and transistor 21 is held off in a period when the potential of node G is low (a period when the potential of node F is high).
Conversely, when a potential of node F falls, charge pump circuit 51 operates in the same manner as charge pump circuit 50 does when a potential of node G falls. When the potential of node F falls from power potential Vcc to the ground potential, a potential of node H also starts to fall by coupling of capacitor 19. In charge pump circuit 50, a potential of node I rises in response to a rise of the potential of node G, so that transistor 22 is turned off. Consequently, a discharging path of capacitor 19 is cut off, and the potential of node H falls to a negative potential (=-Vcc) having the same absolute value as that of power supply potential Vcc. As a result, a potential of node K becomes finally higher than the potential of node H by threshold voltage Vthp (=-Vcc+Vthp). In charge pump circuit 50, transistor 24 is rendered conductive by a fall of the potential of node H of charge pump circuit 51, and node I is brought into the ground potential. Therefore, transistor 23 is turned off. The state in which transistor 23 is held off and transistor 21 outputs a negative voltage (=-Vcc+Vthp) to substrate 130 is maintained in a period when the potential of node F is low (a period when the potential of node G is high).
Two charge pump circuits 50 and 51 shown in FIG. 9 are driven in response to two applied clock signals. Consequently, substrate bias generating circuit 93 generates voltage V.sub.BB (=-Vcc+Vthp) constantly having a negative value.
FIG. 11 is a circuit diagram of substrate bias generating circuit 95 shown in FIG. 8. Referring to FIG. 11, the substrate bias generating circuit 95 receives the ATD pulse generated from ATD circuit 94 as input clock signal .phi.3. Therefore, internal signal /RAS output from RAS input buffer 92 is not applied to circuit 95. ATD circuit 94 outputs ATD pulse .phi.3 in response to a transition of external address signals A0 through An applied to address buffer 81. Since circuit 94 has the same circuit configuration and operates in the same manner as circuit 93 does, the description is not repeated.
As above described, substrate bias generating circuits 93 and 95 are driven in response to applied clock signals .phi.4 and .phi.3, the applied clock signals .phi.4 and .phi.3 have high frequencies, and hence, the following problem arises. First, it should be pointed out that inverters 25 and 26 for shaping a waveform receives input clock signals .phi.4 and .phi.3 having the high frequencies, so that power consumption is increased. Generally, an inverter consumes more current when a state of itself is inverted. This means that the larger the number of repetition of inversion of an inverter is, the more power is consumed. Inverters 25 and 26 shown in FIGS. 9 and 11 are operated in response to clock signals .phi.4 and .phi.3 having high frequencies, so that power consumption of substrate bias generating circuits 93 and 95 is increased.
Secondly, charge pump circuits 50 and 51 perform charge pump operation alternately as described above. It should be also pointed out that efficiency in the charge pump operation is decreased. Capacitors 19 and 20 provided within charge pump circuits 50 and 51 for the charge pump operation repeat charging/discharging. When the frequency of an input clock signal is high, capacitors 19 and 20 cannot perform sufficient charging/discharging. In other words, because charging/discharging of capacitors 19 and 20 are performed in a short clock period, sufficient charging/discharging of capacitors 19 and 20 are not carried out. As a result, charge pump efficiency in charge pump circuits 50 and 51 is decreased.